1. Field of the Invention
The present invention relates generally to semiconductor devices, and more particularly, to a system and method for dynamically adjusting well-bias of transistors in an integrated circuit.
2. Description of the Related Art
As semiconductor processes advance, the size of the devices that can be constructed on a semiconductor substrate continues to grow smaller. With the reduction in device sizes, there is a corresponding reduction in gate oxide thicknesses, and lowered threshold voltage requirements. In addition, as device sizes shrink, the problem with current leaking between devices, and between various device features, is exacerbated. Limiting device leakage currents is important, especially in portable, battery-operated products, where power consumption often dictates product success. Since many handheld products are typically not used for significant periods of time—up to 95% of the time for some products such as cellular phones—controlling the current leakage of semiconductor devices during periods when the product is not in use can result in reduced power consumption.
One method of reducing the leakage current of a semiconductor device is to increase the voltage needed to turn the transistors of the device on. For example, when a complimentary metal oxide semiconductor (CMOS) transistor is to be turned on, enough voltage must be supplied at the gate of the CMOS transistor to allow current to flow between the transistor's source and drain. The amount of voltage needed is called the threshold voltage. In order to ensure that current does not leak between the CMOS transistor's source and drain when the transistor is not in use, a well-bias circuit (e.g., a charge pump) is used to increase the transistor's threshold voltage. As a result of the increased threshold voltage, the leakage current between the transistor's source and drain can be reduced or eliminated.
FIG. 1 shows the substrate of a prior art CMOS integrated circuit (IC) using a well-bias circuit. As shown in FIG. 1, NMOS (n-channel MOS) transistor 101 are formed within P-wells 104, and PMOS (p-channel MOS) transistors 102 are formed within N-wells 106. Each of P-wells 104 and N-wells 106 reside over an electrically insulating substrate region 110. Thus, the substrate isolates the P-wells and N-wells from each other and from all other wells in the substrate.
When either a triple-well, an SOI (silicon-on-insulator) or other well isolating process is used, the P-wells and N-wells can be biased to voltage levels different from each other and from other wells of the same type. An applied voltage differential when applied to a well is referred to as a “well-bias”. As the term is used herein, applying a more positive voltage to a P-well or a more negative voltage to an N-well is called applying a “positive well-bias,” and applying a more negative voltage to a P-well or a more positive voltage to an N-well is called applying a “negative well-bias”.
By changing the voltage level of a well-bias, the threshold voltage (Vt) of the transistors within the well is altered. An increased positive voltage in a P-well or an increased negative voltage in an N-well (i.e., a positive well-bias) causes a drop in the threshold voltage of the NMOS and PMOS transistors within the wells. This lower threshold voltage, in turn, increases the saturation drain current, which increases the performance of all of the transistors within the biased wells. For example, for NMOS transistor 101, a positive well-bias 105 of about 0.4 to 0.6 volts can be applied to P-well 104. Similarly, for PMOS transistor 102, a “positive” well-bias 107 of about −0.4 to −0.6 volts can be applied to an N-well 106. The reverse situation is also true. For example, a lower voltage in a P-well or a higher voltage in N-well 106 (i.e., a negative well-bias) causes a rise in the threshold voltage of the transistors within the well, resulting in a reduced leakage current.
While providing significant advantages in reducing leakage current, a well-bias circuit applying a negative well-bias can also result in problems during operation. In particular, if the negative well-bias voltage is set at a high enough level (magnitude), a significant amount of stress voltage may be placed on the transistor junctions between the gate and wells, and the drains and wells of the transistor. While the application of a negative well-bias will reduce the transistor leakage currents, its application under certain circumstances can create a reliability issue for the circuits. With modern chips being designed for lower supply voltages to reduce IC power consumption, the voltage levels that may cause a stress on transistor junctions are also reduced. When well-bias is applied, the cumulative well-bias and drain-to-source voltages cause various voltage stress effects across the gate-to-body and drain-to-body junctions that reduces component lifetime. As a result, use of a well-bias circuit may, in some cases, raise reliability concerns with regard to the integrated circuits implementing such systems.
What is needed, therefore, is improved circuitry for selectively biasing the well areas of an integrated circuit in a way that reduces voltage stress on the back-biased transistors, thereby increasing the reliability of the integrated circuit.